Refresh rate control for a memory device

ABSTRACT

Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.

CROSS REFERENCE

The present Application for Patent claims is a divisional of U.S. patentapplication Ser. No. 16/786,725, by SCHAEFER et al., entitled “REFRESHRATE CONTROL FOR A MEMORY DEVICE,” filed Feb. 10, 2020, which claims thebenefit of U.S. Provisional Patent Application No. 62/804,469, bySCHAEFER et al., entitled “REFRESH RATE CONTROL FOR A MEMORY DEVICE,”filed Feb. 12, 2019, assigned to the assignee hereof, and each of whichis expressly incorporated by reference herein.

BACKGROUND

The following relates generally to a memory system, and morespecifically to refresh rate control for a memory device.

Memory devices are widely used to store information in variouselectronic devices such as computers, wireless communication devices,cameras, digital displays, and the like. Information is stored byprograming different states of a memory device. For example, binarydevices most often store one of two states, often denoted by a logic 1or a logic 0. In other devices, more than two states may be stored. Toaccess the stored information, a component of the device may read, orsense, at least one stored state in the memory device. To storeinformation, a component of the device may write, or program, the statein the memory device.

Various types of memory devices exist, including magnetic hard disks,random access memory (RAM), read-only memory (ROM), static RAM (SRAM),dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM(FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phasechange memory (PCM), and others. Memory devices may be volatile ornon-volatile. Non-volatile memory, e.g., FeRAM, may maintain theirstored logic state for extended periods of time even in the absence ofan external power source. Volatile memory devices, e.g., SRAM, DRAM, maylose their stored state over time when disconnected from an externalpower source.

For some types of memory (e.g., DRAM, other volatile memory), logicstates stored by memory cells may be occasionally (e.g., periodically)refreshed. Further, in some cases, the amount of time that stored datamay maintain data integrity without refreshing may be related to otherparameters of a memory device. Improving memory devices, generally, mayinclude increasing memory cell density, increasing read/write speeds,increasing reliability, increasing data integrity, reducing powerconsumption, or reducing manufacturing costs, among other metrics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a system that that supports thatsupports refresh rate control for a memory device as disclosed herein.

FIG. 2 illustrates an example of a memory die that supports refresh ratecontrol for a memory device as disclosed herein.

FIG. 3 illustrates an example of a system that supports refresh ratecontrol for a memory device as disclosed herein.

FIGS. 4 through 6 illustrate examples of process flows that supportsrefresh rate control for a memory device as disclosed herein.

FIG. 7 shows a block diagram of a device that supports refresh ratecontrol for a memory device as disclosed herein.

FIGS. 8 through 11 show flowcharts illustrating a method or methods thatsupports refresh rate control for a memory device as disclosed herein.

DETAILED DESCRIPTION

Memory devices may operate under various conditions as part ofelectronic apparatuses such as personal computers, wirelesscommunication devices, servers, internet-of-things (IoT) devices,electronic components of automotive vehicles, and the like. In somecases, memory devices supporting applications for certainimplementations (e.g., automotive vehicles, in some cases withautonomous or semi-autonomous driving capabilities) may be subject toincreased reliability constraints. As such, memory devices (e.g., DRAM)for some applications may be expected to operate with a reliabilitysubject to relatively higher industry standards or specifications (e.g.,higher reliability constraints).

Some memory cells, such as dynamic memory cells, may exhibitdeterioration (loss) of a stored logic state over time. For example,memory cells that utilize a capacitive storage element (e.g., DRAMmemory cells) may lose a stored state or have a stored state change to adifferent state in the event of the capacitive storage element losingsome amount of stored charge, such as due to charge leaking from acapacitor. Without intervention, such as refreshing the logic state byrewriting the memory cell (e.g., recharging the capacitive storageelement), the logic state stored by the memory cell may be lost orcorrupted. One solution is to refresh (rewrite) a memory array every sooften (e.g., at periodic intervals), such as by writing to each memorycell in the array to the logic value stored by the memory cell at thetime the memory cell is refreshed. The desirable rate of refresh for amemory array may depend on a variety of factors, including deterioration(e.g., leakage) rates of memory cells in the array and reliabilitycriteria or constraints for the array. In some cases, (e.g., automotiveapplications), increased reliability of the memory array may be desired(e.g., for critical safety functions). Additionally or alternatively,deterioration rates may vary based on one or more operating conditionsof the memory array. For example, leakage rates for DRAM memory cellsmay increase with temperature, and automotive applications may subjectthe memory array to harsh (e.g., high) temperatures. In another example,leakage rates for DRAM memory cells may increase if voltage conditionsfor the memory device vary (e.g., a power source voltage is reduced).

Techniques for refresh rate control for a memory device are described.For example, the memory device may detect an event at the memory devicethat may be associated with a decrease in data integrity. As a result,the memory device may determine to adjust the refresh rate of the memoryarray to preserve data integrity. The memory device may increase aquantity of rows (e.g., memory cells at one or more physical rows of thememory array) that are refreshed in response to receiving each refreshcommand from a host device. For example, in order to increase therefresh rate by a factor of two (2), the memory device may double thequantity of rows of the memory array that are refreshed in response to asingle refresh command. Additionally or alternatively, the memory devicemay adjust timing parameters. For example, in order to increase therefresh rate of memory array, the memory device may decrease theperiodicity of refresh operations.

Features of the disclosure are further described below in the context ofmemory systems and a memory device with reference to FIGS. 1-3. Featuresof the disclosure are then described in the context of process flowswith reference to FIGS. 4 through 6. These and other features of thedisclosure are further illustrated by and described with reference toapparatus diagrams and flowcharts in FIGS. 7-11 that relate toconfigurable error correction modes.

FIG. 1 illustrates an example of a system 100 that utilizes one or morememory devices in accordance with aspects disclosed herein. The system100 may include an external memory controller 105, a memory device 110,and a plurality of channels 115 coupling the external memory controller105 with the memory device 110. The system 100 may include one or morememory devices, but for ease of description the one or more memorydevices may be described as a single memory device 110.

The system 100 may include aspects of an electronic device, such as acomputing device, a mobile computing device, a wireless device, or agraphics processing device. The system 100 may be an example of aportable electronic device. The system 100 may be an example of acomputer, a laptop computer, a tablet computer, a smartphone, a cellularphone, a wearable device, an internet-connected device, or the like. Thememory device 110 may be component of the system configured to storedata for one or more other components of the system 100. In someexamples, the system 100 is configured for bi-directional wirelesscommunication with other systems or devices using a base station oraccess point. In some examples, the system 100 is capable ofmachine-type communication (MTC), machine-to-machine (M2M)communication, or device-to-device (D2D) communication.

At least portions of the system 100 may be examples of a host device.Such a host device may be an example of a device that uses memory toexecute processes such as a computing device, a mobile computing device,a wireless device, a graphics processing device, a computer, a laptopcomputer, a tablet computer, a smartphone, a cellular phone, a wearabledevice, an internet-connected device, some other stationary or portableelectronic device, or the like. In some cases, the host device may referto the hardware, firmware, software, or a combination thereof thatimplements the functions of the external memory controller 105. In somecases, the external memory controller 105 may be referred to as a hostor host device. In some examples, system 100 is a graphics card.

In some cases, a memory device 110 may be an independent device orcomponent that is configured to be in communication with othercomponents of the system 100 and provide physical memory addresses/spaceto potentially be used or referenced by the system 100. In someexamples, a memory device 110 may be configurable to work with at leastone or a plurality of different types of systems 100. Signaling betweenthe components of the system 100 and the memory device 110 may beoperable to support modulation schemes to modulate the signals,different pin designs for communicating the signals, distinct packagingof the system 100 and the memory device 110, clock signaling andsynchronization between the system 100 and the memory device 110, timingconventions, and/or other factors.

The memory device 110 may be configured to store data for the componentsof the system 100. In some cases, the memory device 110 may act as aslave-type device to the system 100 (e.g., responding to and executingcommands provided by the system 100 through the external memorycontroller 105). Such commands may include an access command for anaccess operation, such as a write command for a write operation, a readcommand for a read operation, a refresh command for a refresh operation,or other commands. The memory device 110 may include two or more memorydice 160 (e.g., memory chips) to support a desired or specified capacityfor data storage. The memory device 110 including two or more memorydice may be referred to as a multi-die memory or package (also referredto as multi-chip memory or package).

The system 100 may further include a processor 120, a basic input/outputsystem (BIOS) component 125, one or more peripheral components 130, andan input/output (I/O) controller 135. The components of system 100 maybe in electronic communication with one another using a bus 140.

The processor 120 may be configured to control at least portions of thesystem 100. The processor 120 may be a general-purpose processor, adigital signal processor (DSP), an application-specific integratedcircuit (ASIC), a field-programmable gate array (FPGA) or otherprogrammable logic device, discrete gate or transistor logic, discretehardware components, or it may be a combination of these types ofcomponents. In such cases, the processor 120 may be an example of acentral processing unit (CPU), a graphics processing unit (GPU), ageneral purpose GPU (GPGPU), or a system on a chip (SoC), among otherexamples.

The BIOS component 125 may be a software component that includes a BIOSoperated as firmware, which may initialize and run various hardwarecomponents of the system 100. The BIOS component 125 may also managedata flow between the processor 120 and the various components of thesystem 100, e.g., the peripheral components 130, the I/O controller 135,etc. The BIOS component 125 may include a program or software stored inread-only memory (ROM), flash memory, or any other non-volatile memory.

The peripheral component(s) 130 may be any input device or outputdevice, or an interface for such devices, that may be integrated into orwith the system 100. Examples may include disk controllers, soundcontroller, graphics controller, Ethernet controller, modem, universalserial bus (USB) controller, a serial or parallel port, or peripheralcard slots, such as peripheral component interconnect (PCI) orspecialized graphics ports. The peripheral component(s) 130 may be othercomponents understood by those skilled in the art as peripherals.

The I/O controller 135 may manage data communication between theprocessor 120 and the peripheral component(s) 130, input 145, or output150. The I/O controller 135 may manage peripherals that are notintegrated into or with the system 100. In some cases, the I/Ocontroller 135 may represent a physical connection or port to externalperipheral components.

The input 145 may represent a device or signal external to the system100 that provides information, signals, or data to the system 100 or itscomponents. This may include a user interface or interface with orbetween other devices. In some cases, the input 145 may be a peripheralthat interfaces with system 100 via one or more peripheral components130 or may be managed by the I/O controller 135.

The output 150 may represent a device or signal external to the system100 configured to receive an output from the system 100 or any of itscomponents. Examples of the output 150 may include a display, audiospeakers, a printing device, or a connection to another processor on aprinted circuit board, and so forth. In some cases, the output 150 maybe a peripheral that interfaces with the system 100 via one or moreperipheral components 130 or may be managed by the I/O controller 135.

The components of system 100 may be made up of general-purpose orspecial purpose circuitry designed to carry out their functions. Thismay include various circuit elements, for example, conductive lines,transistors, capacitors, inductors, resistors, amplifiers, or otheractive or passive elements, configured to carry out the functionsdescribed herein.

The memory device 110 may include a device memory controller 155 and oneor more memory dice 160. Each memory die 160 may include a local memorycontroller 165 (e.g., local memory controller 165-a, local memorycontroller 165-b, and/or local memory controller 165-N) and a memoryarray 170 (e.g., memory array 170-a, memory array 170-b, and/or memoryarray 170-N). A memory array 170 may be a collection (e.g., a grid) ofmemory cells, with each memory cell being configured to store at leastone bit of digital data. Features of memory arrays 170 and/or memorycells are described in more detail with reference to FIG. 2.

The memory device 110 may be an example of a two-dimensional (2D) arrayof memory cells or may be an example of a three-dimensional (3D) arrayof memory cells. For example, a 2D memory device may include a singlememory die 160. A 3D memory device may include two or more memory dice160 (e.g., memory die 160-a, memory die 160-b, and/or any quantity ofmemory dice 160-N). In a 3D memory device, a plurality of memory dice160-N may be stacked on top of one another or next to one another. Insome cases, memory dice 160-N in a 3D memory device may be referred toas decks, levels, layers, or dies. A 3D memory device may include anyquantity of stacked memory dice 160-N (e.g., two high, three high, fourhigh, five high, six high, seven high, eight high). This may increasethe quantity of memory cells that may be positioned on a substrate ascompared with a single 2D memory device, which in turn may reduceproduction costs or increase the performance of the memory array, orboth. In some 3D memory device, different decks may share at least onecommon access line such that some decks may share at least one of a wordline, a digit line, and/or a plate line.

The device memory controller 155 may include circuits or componentsconfigured to control operation of the memory device 110. As such, thedevice memory controller 155 may include the hardware, firmware, andsoftware that enables the memory device 110 to perform commands and maybe configured to receive, transmit, or execute commands, data, orcontrol information related to the memory device 110. The device memorycontroller 155 may be configured to communicate with the external memorycontroller 105, the one or more memory dice 160, or the processor 120.In some cases, the memory device 110 may receive data and/or commandsfrom the external memory controller 105. For example, the memory device110 may receive a write command indicating that the memory device 110 isto store certain data on behalf of a component of the system 100 (e.g.,the processor 120) or a read command indicating that the memory device110 is to provide certain data stored in a memory die 160 to a componentof the system 100 (e.g., the processor 120). In some cases, the devicememory controller 155 may control operation of the memory device 110described herein in conjunction with the local memory controller 165 ofthe memory die 160. Examples of the components included in the devicememory controller 155 and/or the local memory controllers 165 mayinclude receivers for demodulating signals received from the externalmemory controller 105, decoders for modulating and transmitting signalsto the external memory controller 105, logic, decoders, amplifiers,filters, or the like.

The data stored at the memory arrays 170 may, in some cases, becomecorrupted. Corruption of data may refer to an unintentional change ofthe data and thus may refer to an unintended change in the data that isstored by one or more memory cells (e.g., from a logic one (1) to alogic zero (0), or vice versa). A deviation in the value of a bit fromits original and intended value may be referred as an error, a biterror, or a data error. The device memory controller 155 or the localmemory controllers 165 may be configured to internally detect and in atleast some cases correct (repair) such data corruption or errors andthereby recover the data as intended before corruption. For example, aspart of a write operation, the device memory controller 155 or the localmemory controllers 165 may generate one or more error detectioncodewords and store those codewords in an array of memory cells with thedata received from a host device. Upon performing a read operation toretrieve the data, the device memory controller 155 or the local memorycontrollers 165 may also retrieve the error detection codewords andperform error detection or error correction operations to fix certainerrors and/or detect certain errors in the data that may have beenintroduced by the memory device. Such error detection and correction mayrely upon error detection information including one or moreerror-correcting codes (ECCs) (e.g., Hamming codes).

The device memory controller 155 or the local memory controllers 165 maybe configured to employ techniques for refresh rate control for memorydevices 110. The memory device 110 may refresh each memory array 170,where each of the memory cells within the memory array 170 is refreshedaccording to a refresh rate. In some cases, device memory controller 155or the local memory controllers 165 may detect an event (e.g., anextreme temperature, an inadequate voltage supply). The event may beassociated with a decrease in data integrity. The device memorycontroller 155 or the local memory controllers 165 may determine toadjust the refresh rate accordingly (e.g., increase the refresh rate)based on the detected event in order to preserve data integrity.

The local memory controller 165 (e.g., local to a memory die 160) may beconfigured to control operations of the memory die 160. Also, the localmemory controller 165 may be configured to communicate (e.g., receiveand transmit data and/or commands) with the device memory controller155. The local memory controller 165 may support the device memorycontroller 155 to control operation of the memory device 110 asdescribed herein. In some cases, the memory device 110 does not includethe device memory controller 155, and the local memory controller 165 orthe external memory controller 105 may perform the various functionsdescribed herein. As such, the local memory controller 165 may beconfigured to communicate with the device memory controller 155, withother local memory controllers 165, or directly with the external memorycontroller 105 or the processor 120.

The external memory controller 105 may be configured to enablecommunication of information, data, and/or commands between componentsof the system 100 (e.g., the processor 120) and the memory device 110.The external memory controller 105 may act as a liaison between thecomponents of the system 100 and the memory device 110 so that thecomponents of the system 100 may not need to know the details of thememory device's operation. In some cases, the external memory controller105 may be an example of a GPU. The components of the system 100 maypresent requests to the external memory controller 105 (e.g., readcommands or write commands) that the external memory controller 105satisfies. The external memory controller 105 may convert or translatecommunications exchanged between the components of the system 100 andthe memory device 110. In some cases, the external memory controller 105may include a system clock that generates a common (source) system clocksignal. In some cases, the external memory controller 105 may include acommon data clock that generates a common (source) data clock signal.

In some cases, the external memory controller 105 or other component ofthe system 100, or its functions described herein, may be implemented bythe processor 120. For example, the external memory controller 105 maybe hardware, firmware, or software, or some combination thereofimplemented by the processor 120 or other component of the system 100.While the external memory controller 105 is depicted as being externalto the memory device 110, in some cases, the external memory controller105, or its functions described herein, may be implemented by a memorydevice 110. For example, the external memory controller 105 may behardware, firmware, or software, or some combination thereof implementedby the device memory controller 155 or one or more local memorycontrollers 165. In some cases, the external memory controller 105 maybe distributed across the processor 120 and the memory device 110 suchthat portions of the external memory controller 105 are implemented bythe processor 120 and other portions are implemented by a device memorycontroller 155 or a local memory controller 165. Likewise, in somecases, one or more functions ascribed herein to the device memorycontroller 155 or local memory controller 165 may in some cases beperformed by the external memory controller 105 (either separate from oras included in the processor 120).

The components of the system 100 may exchange information with thememory device 110 using a plurality of channels 115. In some examples,the channels 115 may enable communications between the external memorycontroller 105 and the memory device 110. Each channel 115 may includeone or more signal paths or transmission mediums (e.g., conductors)between terminals associated with the components of system 100. Forexample, a channel 115 may include a first terminal including one ormore pins or pads at external memory controller 105 and one or more pinsor pads at the memory device 110. A pin may be an example of aconductive input or output point of a device of the system 100, and apin may be configured to act as part of a channel.

In some cases, a pin or pad of a terminal may be part of a signal pathof the channel 115. Additional signal paths may be coupled with aterminal of a channel for routing signals within a component of thesystem 100. For example, the memory device 110 may include signal paths(e.g., signal paths internal to the memory device 110 or its components,such as internal to a memory die 160) that route a signal from aterminal of a channel 115 to the various components of the memory device110 (e.g., a device memory controller 155, memory dice 160, local memorycontrollers 165, memory arrays 170).

Channels 115 (and associated signal paths and terminals) may bededicated to communicating specific types of information. In some cases,a channel 115 may be an aggregated channel and thus may include multipleindividual channels. For example, a data channel 190 may be x4 (e.g.,including four signal paths), x8 (e.g., including eight signal paths),x16 (including sixteen signal paths), and so forth. Signals communicatedover the channels may use double data rate (DDR) signaling. For example,some symbols of a signal may be registered on a rising edge of a clocksignal and other symbols of the signal may be registered on a fallingedge of the clock signal. Signals communicated over channels may usesingle data rate (SDR) signaling. For example, one symbol of the signalmay be registered for each clock cycle.

In some cases, the channels 115 may include one or more command andaddress (CA) channels 186. The CA channels 186 may be configured tocommunicate commands between the external memory controller 105 and thememory device 110 including control information associated with thecommands (e.g., address information). For example, the CA channel 186may include a read command with an address of the desired data. In somecases, the CA channels 186 may be registered on a rising clock signaledge and/or a falling clock signal edge. In some cases, a CA channel 186may include any quantity of signal paths to decode address and commanddata (e.g., eight or nine signal paths).

In some cases, the channels 115 may include one or more clock signal(CK) channels 188. The CK channels 188 may be configured to communicateone or more common clock signals between the external memory controller105 and the memory device 110. Each clock signal may be configured tooscillate between a high state and a low state and coordinate theactions of the external memory controller 105 and the memory device 110.In some cases, the clock signal may be a differential output (e.g., aCK_t signal and a CK_c signal) and the signal paths of the CK channels188 may be configured accordingly. In some cases, the clock signal maybe single ended. A CK channel 188 may include any quantity of signalpaths. In some cases, the clock signal CK (e.g., a CK_t signal and aCK_c signal) may provide a timing reference for command and addressingoperations for the memory device 110, or other system-wide operationsfor the memory device 110. The clock signal CK therefore may bevariously referred to as a control clock signal CK, a command clocksignal CK, or a system clock signal CK. The system clock signal CK maybe generated by a system clock, which may include one or more hardwarecomponents (e.g., oscillators, crystals, logic gates, transistors, orthe like).

In some cases, the channels 115 may include one or more data (DQ)channels 190. The data channels 190 may be configured to communicatedata and/or control information between the external memory controller105 and the memory device 110. For example, the data channels 190 maycommunicate information (e.g., bi-directional) to be written to thememory device 110 or information read from the memory device 110. Thedata channels 190 may communicate signals that may be modulated using avariety of different modulation schemes (e.g., NRZ, PAM4).

In some cases, the channels 115 may include one or more other channels192 that may be dedicated to other purposes. These other channels 192may include any quantity of signal paths.

In some cases, the other channels 192 may include one or more writeclock signal (WCK) channels. While the ‘W’ in WCK may nominally standfor “write,” a write clock signal WCK (e.g., a WCK_t signal and a WCK_csignal) may provide a timing reference for access operations generallyfor the memory device 110 (e.g., a timing reference for both read andwrite operations). Accordingly, the write clock signal WCK may also bereferred to as a data clock signal WCK. The WCK channels may beconfigured to communicate a common data clock signal between theexternal memory controller 105 and the memory device 110. The data clocksignal may be configured to coordinate an access operation (e.g., awrite operation or read operation) of the external memory controller 105and the memory device 110. In some cases, the write clock signal may bea differential output (e.g., a WCK_t signal and a WCK_c signal) and thesignal paths of the WCK channels may be configured accordingly. A WCKchannel may include any quantity of signal paths. The data clock signalWCK may be generated by a data clock, which may include one or morehardware components (e.g., oscillators, crystals, logic gates,transistors, or the like).

In some cases, the other channels 192 may include one or more errordetection code (EDC) channels. The EDC channels may be configured tocommunicate error detection signals, such as checksums, to improvesystem reliability. An EDC channel may include any quantity of signalpaths.

The channels 115 may couple the external memory controller 105 with thememory device 110 using a variety of different architectures. Examplesof the various architectures may include a bus, a point-to-pointconnection, a crossbar, a high-density interposer such as a siliconinterposer, or channels formed in an organic substrate or somecombination thereof. For example, in some cases, the signal paths may atleast partially include a high-density interposer, such as a siliconinterposer or a glass interposer.

Signals communicated over the channels 115 may be modulated using avariety of different modulation schemes. In some cases, a binary-symbol(or binary-level) modulation scheme may be used to modulate signalscommunicated between the external memory controller 105 and the memorydevice 110. A binary-symbol modulation scheme may be an example of aM-ary modulation scheme where M is equal to two. Each symbol of abinary-symbol modulation scheme may be configured to represent one bitof digital data (e.g., a symbol may represent a logic 1 or a logic 0).Examples of binary-symbol modulation schemes include, but are notlimited to, non-return-to-zero (NRZ), unipolar encoding, bipolarencoding, Manchester encoding, pulse amplitude modulation (PAM) havingtwo symbols (e.g., PAM2), and/or others.

In some cases, a multi-symbol (or multi-level) modulation scheme may beused to modulate signals communicated between the external memorycontroller 105 and the memory device 110. A multi-symbol modulationscheme may be an example of a M-ary modulation scheme where M is greaterthan or equal to three. Each symbol of a multi-symbol modulation schememay be configured to represent more than one bit of digital data (e.g.,a symbol may represent a logic 00, a logic 01, a logic 10, or a logic11). Examples of multi-symbol modulation schemes include, but are notlimited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM),quadrature phase shift keying (QPSK), and/or others. A multi-symbolsignal or a PAM4 signal may be a signal that is modulated using amodulation scheme that includes at least three levels to encode morethan one bit of information. Multi-symbol modulation schemes and symbolsmay alternatively be referred to as non-binary, multi-bit, orhigher-order modulation schemes and symbols.

FIG. 2 illustrates an example of a memory die 200 in accordance withvarious examples disclosed herein. The memory die 200 may be an exampleof the memory dice 160 described with reference to FIG. 1. In somecases, the memory die 200 may be referred to as a memory chip, a memorydevice, or an electronic memory apparatus. The memory die 200 mayinclude one or more memory cells 205 that are programmable to storedifferent logic states. Each memory cell 205 may be programmable tostore two or more states. For example, the memory cell 205 may beconfigured to store one bit of digital logic at a time (e.g., a logic 0and a logic 1). In some cases, a single memory cell 205 (e.g., amulti-level memory cell) may be configured to store more than one bit ofdigit logic at a time (e.g., a logic 00, logic 01, logic 10, or a logic11).

A memory cell 205 may store a charge representative of the programmablestates in a capacitor. DRAM architectures may include a capacitor thatincludes a dielectric material to store a charge representative of theprogrammable state. In other memory architectures, other storage devicesand components are possible. For example, nonlinear dielectric materialsmay be employed.

Operations such as reading and writing may be performed on memory cells205 by activating or selecting access lines such as a word line 210and/or a digit line 215. In some cases, digit lines 215 may also bereferred to as bit lines. References to access lines, word lines anddigit lines, or their analogues, are interchangeable without loss ofunderstanding or operation. Activating or selecting a word line 210 or adigit line 215 may include applying a voltage to the respective line.

The memory die 200 may include the access lines (e.g., the word lines210 and the digit lines 215) arranged in a grid-like pattern. Memorycells 205 may be positioned at intersections of the word lines 210 andthe digit lines 215. By biasing a word line 210 and a digit line 215(e.g., applying a voltage to the word line 210 or the digit line 215), asingle memory cell 205 may be accessed at their intersection.

Accessing the memory cells 205 may be controlled through a row decoder220 or a column decoder 225. For example, a row decoder 220 may receivea row address from the local memory controller 260 and activate a wordline 210 based on the received row address. A column decoder 225 mayreceive a column address from the local memory controller 260 and mayactivate a digit line 215 based on the received column address. Forexample, the memory die 200 may include multiple word lines 210, labeledWL_1 through WL_M, and multiple digit lines 215, labeled DL_1 through DLN, where M and N depend on the size of the memory array. Thus, byactivating a word line 210 and a digit line 215, e.g., WL_1 and DL_3,the memory cell 205 at their intersection may be accessed. Theintersection of a word line 210 and a digit line 215, in either atwo-dimensional or three-dimensional configuration, may be referred toas an address of a memory cell 205.

The memory cell 205 may include a logic storage component, such ascapacitor 230 and a switching component 235. The capacitor 230 may be anexample of a dielectric capacitor or a ferroelectric capacitor. A firstnode of the capacitor 230 may be coupled with the switching component235 and a second node of the capacitor 230 may be coupled with a voltagesource 240. In some cases, the voltage source 240 may be the cell platereference voltage, such as Vpl, or may be ground, such as Vss. In somecases, the voltage source 240 may be an example of a plate line coupledwith a plate line driver. The switching component 235 may be an exampleof a transistor or any other type of switch device that selectivelyestablishes or de-establishes electronic communication between twocomponents.

Selecting or deselecting the memory cell 205 may be accomplished byactivating or deactivating the switching component 235. The capacitor230 may be in electronic communication with the digit line 215 using theswitching component 235. For example, the capacitor 230 may be isolatedfrom digit line 215 when the switching component 235 is deactivated, andthe capacitor 230 may be coupled with digit line 215 when the switchingcomponent 235 is activated. In some cases, the switching component 235is a transistor and its operation may be controlled by applying avoltage to the transistor gate, where the voltage differential betweenthe transistor gate and transistor source may be greater or less than athreshold voltage of the transistor. In some cases, the switchingcomponent 235 may be a p-type transistor or an n-type transistor. Theword line 210 may be in electronic communication with the gate of theswitching component 235 and may activate/deactivate the switchingcomponent 235 based on a voltage being applied to word line 210.

A word line 210 may be a conductive line in electronic communicationwith a memory cell 205 that is used to perform access operations on thememory cell 205. In some architectures, the word line 210 may be inelectronic communication with a gate of a switching component 235 of amemory cell 205 and may be configured to control the switching component235 of the memory cell. In some architectures, the word line 210 may bein electronic communication with a node of the capacitor of the memorycell 205 and the memory cell 205 may not include a switching component.

A digit line 215 may be a conductive line that connects the memory cell205 with a sense component 245. In some architectures, the memory cell205 may be selectively coupled with the digit line 215 during portionsof an access operation. For example, the word line 210 and the switchingcomponent 235 of the memory cell 205 may be configured to couple and/orisolate the capacitor 230 of the memory cell 205 and the digit line 215.In some architectures, the memory cell 205 may be in electroniccommunication (e.g., constant) with the digit line 215.

The sense component 245 may be configured to detect a state (e.g., acharge) stored on the capacitor 230 of the memory cell 205 and determinea logic state of the memory cell 205 based on the stored state. Thecharge stored by a memory cell 205 may be extremely small, in somecases. As such, the sense component 245 may include one or more senseamplifiers to amplify the signal output by the memory cell 205. Thesense amplifiers may detect small changes in the charge of a digit line215 during a read operation and may produce signals corresponding to alogic state 0 or a logic state 1 based on the detected charge. During aread operation, the capacitor 230 of memory cell 205 may output a signal(e.g., discharge a charge) to its corresponding digit line 215. Thesignal may cause a voltage of the digit line 215 to change. The sensecomponent 245 may be configured to compare the signal received from thememory cell 205 across the digit line 215 to a reference signal 250(e.g., reference voltage). The sense component 245 may determine thestored state of the memory cell 205 based on the comparison.

For example, in binary-signaling, if digit line 215 has a higher voltagethan the reference signal 250, the sense component 245 may determinethat the stored state of memory cell 205 is a logic 1 and, if the digitline 215 has a lower voltage than the reference signal 250, the sensecomponent 245 may determine that the stored state of the memory cell 205is a logic 0. The sense component 245 may include various transistors oramplifiers to detect and amplify a difference in the signals. Thedetected logic state of memory cell 205 may be output through columndecoder 225 as output 255. In some cases, the sense component 245 may bepart of another component (e.g., a column decoder 225, row decoder 220).In some cases, the sense component 245 may be in electroniccommunication with the row decoder 220 or the column decoder 225.

The local memory controller 260 may control the operation of memorycells 205 through the various components (e.g., row decoder 220, columndecoder 225, and sense component 245). The local memory controller 260may be an example of the local memory controller 165 described withreference to FIG. 1. In some cases, one or more of the row decoder 220,column decoder 225, and sense component 245 may be co-located with thelocal memory controller 260.

The local memory controller 260 may be configured to receive commandsand/or data from an external memory controller 105 (or a device memorycontroller 155 described with reference to FIG. 1), translate thecommands and/or data into information that can be used by the memory die200, perform one or more operations on the memory die 200, andcommunicate data from the memory die 200 to the external memorycontroller 105 (or the device memory controller 155) in response toperforming the one or more operations. The local memory controller 260may generate row and column address signals to activate the target wordline 210 and the target digit line 215. The local memory controller 260may also generate and control various voltages or currents used duringthe operation of the memory die 200. In general, the amplitude, shape,or duration of an applied voltage or current discussed herein may beadjusted or varied and may be different for the various operationsdiscussed in operating the memory die 200.

In some cases, the local memory controller 260 may be configured toperform a write operation (e.g., a programming operation) on one or morememory cells 205 of the memory die 200. During a write operation, amemory cell 205 of the memory die 200 may be programmed to store adesired logic state. In some cases, a plurality of memory cells 205 maybe programmed during a single write operation. The local memorycontroller 260 may identify a target memory cell 205 on which to performthe write operation.

The local memory controller 260 may identify a target word line 210 anda target digit line 215 in electronic communication with the targetmemory cell 205 (e.g., the address of the target memory cell 205). Thelocal memory controller 260 may activate the target word line 210 andthe target digit line 215 (e.g., applying a voltage to the word line 210or digit line 215), to access the target memory cell 205. The localmemory controller 260 may apply a specific signal (e.g., voltage) to thedigit line 215 during the write operation to store a specific state(e.g., charge) in the capacitor 230 of the memory cell 205, the specificstate (e.g., charge) may be indicative of a desired logic state.

In some cases, the local memory controller 260 may be configured toperform a read operation (e.g., a sense operation) on one or more memorycells 205 of the memory die 200. During a read operation, the logicstate stored in a memory cell 205 of the memory die 200 may bedetermined. In some cases, a plurality of memory cells 205 may be sensedduring a single read operation. The local memory controller 260 mayidentify a target memory cell 205 on which to perform the readoperation. The local memory controller 260 may identify a target wordline 210 and a target digit line 215 in electronic communication withthe target memory cell 205 (e.g., the address of the target memory cell205). The local memory controller 260 may activate the target word line210 and the target digit line 215 (e.g., applying a voltage to the wordline 210 or digit line 215), to access the target memory cell 205. Thetarget memory cell 205 may transfer a signal to the sense component 245in response to biasing the access lines. The sense component 245 mayamplify the signal. The local memory controller 260 may fire the sensecomponent 245 (e.g., latch the sense component) and thereby compare thesignal received from the memory cell 205 to the reference signal 250.

Based on that comparison, the sense component 245 may determine a logicstate that is stored on the memory cell 205. The local memory controller260 may communicate the logic state stored on the memory cell 205 to theexternal memory controller 105 (or the device memory controller 155) aspart of the read operation.

In some memory architectures, accessing the memory cell 205 may degradeor destroy the logic state stored in a memory cell 205. For example, aread operation performed in DRAM architectures may partially orcompletely discharge the capacitor of the target memory cell. The localmemory controller 260 may perform a re-write operation or a refreshoperation to return the memory cell to its original logic state. Thelocal memory controller 260 may re-write the logic state to the targetmemory cell after a read operation. In some cases, the re-writeoperation may be considered part of the read operation. Additionally,activating a single access line, such as a word line 210, may disturbthe state stored in some memory cells in electronic communication withthat access line. Thus, a re-write operation or refresh operation may beperformed on one or more memory cells that may not have been accessed.

The local memory controller 260 may operate according to either anautomatic refresh mode or a self-refresh mode. In an automatic refreshmode, the local memory controller 260 may receive refresh commands forrefreshing the memory die 200 from a host device (e.g., from externalmemory controller 105). The automatic refresh mode may be used in afirst operation mode (e.g., a default operation) of the memory devicewhere the memory device receives and executes memory commands. In theautomatic refresh mode, the local memory controller 260 may perform arefresh operation when it receives each refresh command, where eachrefresh operation includes refreshing one or more rows of the memoryarray.

In a self-refresh mode, the local memory controller 260 may initiate therefresh operations. The self-refresh mode may be used in a low-power orstandby state of the memory device, where the memory device may notreceive memory commands including refresh commands. In self-refreshmode, the local memory controller 260 may refresh memory cells 205 usingan internal oscillator, internal counters, or the like. In either mode,the local memory controller 260 may determine a refresh rate accordingto the conditions of the memory die 200. The refresh rate may correspondto the inverse of a periodicity that each of the memory cells 205 arerefreshed.

The local memory controller 260 may detect an event at the memory device(e.g., an event associated with a decrease in data integrity). As aresult, the local memory controller 260 may determine to adjust therefresh rate of the memory die 200 to preserve data integrity. When thelocal memory controller 260 is operating according to an automaticrefresh mode, the local memory controller 260 may increase a quantity ofrows (e.g., memory cells at one or more physical rows of the memory die200) that are refreshed in response to receiving each refresh commandfrom a host device.

For example, in order to increase the refresh rate by a factor of two(2), the local memory controller 260 may double the quantity of rows ofthe memory die 200 that are refreshed in response to a single refreshcommand. When the local memory controller 260 is operating according toa self-refresh mode, the local memory controller 260 may adjust timingparameters or a quantity of rows of the memory die 200 that arerefreshed in a single refresh operation. For example, in order toincrease the refresh rate of memory die 200, the local memory controller260 may decrease the periodicity of refresh operations or may increase aquantity of rows of the memory die 200 that are refreshed during theexecution of a single refresh operation, or may adjust both parametersin combination.

FIG. 3 illustrates an example of a system 300 that supports techniquesfor refresh rate control for a memory device. The system 300 may includeone or more components described herein with reference to FIGS. 1 and 2,among others. For example, the system 300 may include a host device 305,which may be an example of the external memory controller 105 asdescribed with reference to FIG. 1; a memory device 310, which may be anexample of the memory device 110, the memory dice 160, or the memory die200 as described with reference to FIGS. 1 and 2; a controller 320,which may be an example of the device memory controller 155, one or morelocal memory controllers 165, or the local memory controller 260 asdescribed with reference to FIGS. 1 and 2, or any combination thereof; amemory array 325, which may be an example of the memory arrays 170 asdescribed with reference to FIG. 1. The memory device 310 may alsoinclude an event detection circuit 330.

Host device 305 may send commands to memory device 310, which may bereceived via the memory interface 315. The commands may include refreshcommands to perform one or more refresh operations (e.g., refreshingmemory cells at one or more physical rows of memory array 325). Thecontroller 320 may receive commands from the memory interface 315,process the commands, and execute the commands on memory array 325.Controller 320 may operate the memory array 325 according to variousmodes of operation. For example, controller 320 may operate the memoryarray 325 according to an automatic refresh mode or a self-refresh mode.

Memory array 325 may include one or more memory banks, each of which mayinclude one or more rows and/or one or more columns. In some cases, upondetermining to perform one or more refresh operations, controller 320may initiate refresh of memory cells at one or more physical locations(e.g., rows, columns, etc.). The refresh operation may specify anaddress for refresh (e.g., a row address), and memory device 310 (e.g.,controller 320) may determine one or more additional addresses forrefresh according to an internal counter (e.g., by incrementing a rowaddress counter so as to obtain one or more additional row addresses).In this regard, one or more refresh operations may be initiated bycontroller 320. The controller 320 may initiate a refresh operationbased on receiving refresh commands from host device 305 (e.g., duringan automatic refresh mode) or based on generating the refresh operationat the controller 320 (e.g., during a self-refresh mode). The controller320 may refresh the corresponding (e.g., as specified or determinedbased on the refresh operation) memory cells within the memory array325.

The memory device 310 may perform a series of refresh operations untilall rows of memory array 325 have been refreshed. The refresh operationsmay be performed at multiple physical locations (e.g., multiple rows)concurrently (e.g., for different banks or sub-arrays), offset accordingto some pattern (e.g., different rows at different times), or the like.In some cases, the controller 320 may perform the refresh operationsinterspersed with other accesses of memory array 325 (e.g., read, write,etc.). The periodicity of refresh operations (e.g., how often thecontroller 320 initiates a refresh operation) combined with the quantityof rows refreshed in response to each refresh operation may determine arefresh rate for the memory array 325 (e.g., the inverse of theperiodicity that each of the memory cells of the memory array 325 arerefreshed). Upon initialization (e.g., power up), the memory device 310may be configured to perform refresh operations according to a defaultrefresh configuration. The default refresh configuration may include thememory device 310 operating according to a set of refresh parameters(e.g., a refresh rate, a refresh periodicity, a quantity of rowsrefreshed during each refresh operation) defined prior to initializationof the memory device 310.

The controller 320 may dynamically determine a refresh rate for thememory array 325 based on the data integrity of the memory array 325. Insome cases, the memory array 325 may have a refresh rate parameterindicated by an industry standard or specification, where the controller320 may ensure that the refresh rate is equal to or faster than theindicated refresh rate. In some other cases, the memory array 325 maydetect an event. For example, certain events may impact data integrity(e.g., decrease the data integrity) of the memory array 325.

In some cases, the memory array 325 may exhibit higher data integritywhen operating within a nominal temperature range (e.g., including roomtemperature) than when the event detection circuit 330 detects anextreme temperature at the memory device 310 (e.g., a temperaturesignificantly higher or lower than room temperature). In a secondexample, the memory array 325 may exhibit lower data integrity whencertain voltage events are detected at the memory device 310 (e.g., inthe event that a power supply voltage is low or unstable). As a resultof the detected event, the controller 320 may determine to adjust therefresh rate of the memory array 325.

The event detection circuit 330 may detect events that affect the dataintegrity of the memory array 325. For example, the event detectioncircuit 330 may detect a temperature of the memory device 310. The eventdetection circuit 330 may detect an event associated with decreased dataintegrity when the temperature of the memory device 310 exceeds acertain threshold (e.g., the temperature of the memory device 310 is toohigh or too low). In a second example, the event detection circuit 330may measure certain voltage levels of the memory device 310 (e.g., avoltage level of a power supply for the memory device 310). The eventdetection circuit 330 may detect an event associated with decreased dataintegrity if a measured voltage level goes below a threshold voltagelevel (e.g., for a certain time or a certain quantity of times within atime period).

In a third example, the event detection circuit 330 may detect aquantity of error events at the memory array 325. For example, thecontroller 320 may perform error detection or error correctionoperations during read and write operations to correct bit errors at thememory array 325. The event detection circuit 330 may monitor a quantityof error correction operations and error detections at the memory array325 and may detect an event associated with decreased data integrity ifa quantity of errors (e.g., corrected and/or detected) exceeds athreshold quantity. The threshold quantity may correspond to a quantityof errors detected within a certain time period (e.g., a maximumquantity of errors within a one (1) second window), within a certainportion of the memory array 325 (e.g., a maximum quantity of errors froma row or group of rows of the memory array 325), a certain quantity ofsingle-bit errors, a certain quantity of multi-bit errors, or acombination thereof.

In a fourth example, the event detection circuit 330 may determine thatthe refresh operations do not satisfy an industry standard orspecification for the memory device 310 (e.g., the refresh operations donot satisfy a refresh rate parameter). Here, the event detection circuit330 may determine a current refresh rate (e.g., the time it takes torefresh the memory array 325 based on a current refresh operationexecution periodicity in combination with a quantity of rows of thememory array 325 that are refreshed during the execution of each refreshoperation) and compare the current refresh rate to the refresh rateparameter. The event detection circuit 330 may detect an eventassociated with decreased data integrity if the current refresh rate isless than the refresh rate parameter. In the case that the memory device310 is operating according to an automatic refresh mode, the eventdetection circuit 330 may determine a current refresh rate based on thecurrent periodicity of received refresh commands and compare thisrefresh rate to the refresh rate parameter.

For example, the event detection circuit 330 may determine that, basedon the quantity of rows of the memory array 325 that are refreshedduring the execution of each operation, a certain quantity R of refreshoperations may refresh the memory array 325. The refresh rate parametermay be to receive the R refresh commands with in a time period T. Theevent detection circuit 330 may determine that the current refreshcommand periodicity may not cause the memory array 325 to receive Rrefresh commands within the time period T. In some cases, the eventdetection circuit 330 may make a predictive determination based on somefractions of R and T. For example, the event detection circuit 330 maydetect that R/2 refresh commands have not been received within a timeperiod of T/2. Additionally or alternatively, the event detectioncircuit 330 may determine that a remaining time period in a refreshcycle having a period T is insufficient to complete refreshing all rowsof the array. For example, the event detection circuit 330 may determinethat, based on a quantity R₁ of refresh commands received in a timeperiod T₁, where T₁<T, it is not feasible or likely to receive R−R₁refresh commands in the time period T−T₁. Here, the event detectioncircuit 330 may detect an event associated with decreased dataintegrity.

In a fifth example, the event detection circuit 330 may detect a healthof various components within the memory device 310. For example, theevent detection circuit 330 may detect a degradation of a row detectioncircuit or a sense amplifier of the memory device, which may in turnresult in the event detection circuit 330 detecting an event associatedwith a decrease in data integrity. The event detection circuit 330 maydetect a degradation of certain components based on a quantity of errorcorrection operations and a quantity of error detections correspondingto certain portions of the memory array 325 (e.g., certain rows,columns, sub-arrays). The event detection circuit 330 may determine if aquantity of error correction operations and a quantity of errordetections corresponding to a portion of the memory array 325 fallsbelow a threshold. In the event that the quantity of error correctionoperations and error detections is above the threshold, the eventdetection circuit 330 may detect an event associated with decreased dataintegrity.

The thresholds (e.g., for detecting events associated with decreaseddata integrity) may be preconfigured at the memory device 310.Additionally or alternatively, the thresholds may be indicated (e.g.,via the memory interface 315) by the host device 305. In some cases, thethresholds may be codependent. That is, the thresholds for events (e.g.,temperature events, voltage events, error events) may be based on thecombination of multiple detected events. For example, if the eventdetection circuit 330 detects a first temperature at the memory array325, the event detection circuit 330 may not detect an event associatedwith a decreased data integrity. However, if the event detection circuit330 detects the first temperature in combination with a voltagecondition (e.g., a low voltage supply condition), the event detectioncircuit 330 may detect an event associated with a decreased dataintegrity.

In the event that the event detection circuit 330 detects an eventassociated with decreased data integrity for the memory array 325, theevent detection circuit 330 may indicate (e.g., flag) the event to thecontroller 320. In some cases, the event detection circuit 330 maytransmit a notification of the event to the controller 320 when theevent is detected.

Alternatively, the controller 320 may poll a flag set by the eventdetection circuit 330 prior to executing a refresh operation todetermine any detected events. The controller 320 may adapt the refreshrate of the memory array 325 based on receiving an indication of theevent from the event detection circuit 330. In a case when thecontroller 320 is operating according to an automatic refresh mode, thecontroller 320 may adapt a quantity of rows executed per refresh command(e.g., as received from the host device 305). For example, thecontroller 320 may receive an indication of an event from the eventdetection circuit 330 and determine to increase the refresh rate of thememory array 325 and increase the quantity of rows refreshed per refreshcommand (e.g., from four rows to six, eight, ten, twelve, or sixteenrows). In the case when the controller 320 is operation according to aself-refresh mode, the controller 320 may adapt a periodicity of therefresh operations and/or the quantity of rows refreshed per refreshoperation.

When the controller 320 adapts the refresh rate of the memory array 325,the controller 320 may transmit a notification of the adapted refreshrate to the host device 305. The notification may indicate the adaptedrefresh status (e.g., that the refresh rate has been adapted).Additionally or alternatively, the notification may indicate the eventdetected by the event detection circuit 330. In some cases, thenotification may be communicated by the memory interface 315. Forexample, the memory device 310 may transmit the notification by a pin ofthe memory interface 315. In some cases, the pin may be multifunctional(e.g., used to transmit data or other types of signaling as well). Insome other cases, the pin may be dedicated for the notification. Inanother example, the memory device 310 may transmit the notification bya sideband communication scheme (e.g., by a communication bus other thanthe memory data interface such as an inter-integrated circuit (I²C)bus).

The host device 305 may detect the notification and determine whether toreset the memory device 310. Resetting the memory device 310 may includethe memory device 310 adapting the refresh parameters (e.g., refreshoperation periodicity, a quantity of rows refreshed per refreshoperation) based on a notification received from the host device 305.For example, the host device 305 may determine to reset the memorydevice 310 to the previous refresh parameters (e.g., the parametersutilized prior to adapting the refresh parameters based on detection theevent associated with a decrease in data integrity). If the host device305 determines to reset the memory device 310, the host device 305 maytransmit a notification to the memory device 310. Based on receiving thereset notification, the memory device 310 may adapt the refreshparameters for the memory device 310.

FIG. 4 shows an example diagram of a process flow 400 that supportstechniques for refresh rate control for a memory device. The features ofprocess flow 400 may be implemented or performed by a memory device(e.g., the memory device 110, the memory dice 160, the memory die 200,or the memory device 310 described with reference to FIGS. 1 through 3,among others) or a component of a memory device such as the devicememory controller 155, the local memory controllers 165, the localmemory controller 260, the controller 320, or the refresh detectioncircuit 335 as described with reference to FIGS. 1 through 3.

At 405, a memory device may be operating according to a default refreshconfiguration. The default refresh configuration may include the memorydevice operating according to some preconfigured refresh parameters(e.g., a refresh periodicity, a quantity of rows refreshed during eachrefresh operation, and/or a refresh rate). The memory device may beoperating according to an automatic refresh mode or a self-refresh mode.The automatic refresh mode may include the memory device executingrefresh operations based on a refresh commands received from a hostdevice (e.g., according to a refresh periodicity defined by aperiodicity of the refresh commands). The self-refresh mode may includethe memory device executing refresh operations based on self-generatedrefresh operations (e.g., by a controller at the memory device and basedon an internal clock).

At 410, the memory device may determine whether an event (e.g.,associated with decreased data integrity) is detected at the memorydevice. For example, the event detection circuit 330 (e.g., as describedwith reference to FIG. 3) may determine that a temperature threshold forthe memory device has been exceeded. In some other cases, the memorydevice may detect an event related to a voltage level of the memorydevice, errors at a memory array of the memory device, component health,or not meeting a parameter indicated by an industry standard orspecification for the memory device. The memory device may detect theevents based on determining if a threshold has been satisfied.

For example, the memory device may detect an event in the case that atemperature threshold has been satisfied (e.g., the temperature of thememory device is higher or lower than a temperature threshold). Inanother example, the memory device may detect an event in the case thata voltage level for the memory device has been satisfied (e.g., thepower supply for the memory device falls below a threshold, is below thethreshold for a certain period of time, or falls below the threshold acertain quantity of times within a time period). In some cases, thethresholds may adapt based on a combination of detected events. Forexample, the temperature threshold may adjust based on a temperaturetrend (e.g., the maximum temperature threshold may decrease if thetemperature level is quickly rising). In another example, the thresholdvoltage corresponding to a minimum voltage level supplied to the memorydevice may increase in the event that the temperature of the memorydevice approaches a temperature threshold.

In some cases, the event detection circuit 330 may generate one or morebits indicative of the event associated with decreased data integrityand transmit the indication to a controller associated with the memorydevice (e.g., the controller 320 as discussed with reference to FIG. 3).In some other cases, the controller associated with the memory devicemay poll the event detection circuit 330 at a certain periodicity todetermine if the event has been detected. For example, the controllermay poll the event detection circuit 330 prior to executing each refreshcommand.

In a first case, the memory device may determine at block 410 that therewas not an event associated with a decreased data integrity detected atthe memory device. Here, the memory device may continue to operateaccording to the default refresh operation (e.g., as described at 405).

In a second case, the memory device may determine at block 410 that theevent associated with decreased data integrity is detected. Here, thememory device may proceed to block 415. At block 415, the memory devicemay transmit signaling to the host device indicating that the memorydevice will begin executing refresh commands according to an alternativerefresh configuration associated with a different refresh rate.Additionally or alternatively, the memory device may indicate the eventdetected by the event detection circuit 330. The memory device mayindicate the alternative refresh configuration by a pin at a memoryinterface of the memory device. In some cases, the pin may bemultifunctional (e.g., used to transmit data as well). In some othercases, the pin may be dedicated for the notification. In anotherexample, the memory device may transmit the notification by a sidebandcommunication scheme.

At 420, the memory device may adapt to operate according to analternative refresh configuration which may be associated with adifferent refresh rate (e.g., when compared to the default refreshconfiguration). In a case when the memory device is operating accordingto an automatic refresh mode, the memory device may adapt a quantity ofrows executed per refresh command (e.g., as received from the hostdevice). For example, the alternative refresh operation may have refreshrate that is increased by a factor (e.g., 2x, 3x, 4x), and the memorydevice may increase a quantity of rows refreshed per refresh commandfrom based on the factor. In the case when the memory device isoperating according to a self-refresh mode, the memory device may adapta periodicity of the refresh operations and/or the quantity of rowsrefreshed per refresh operation. For example, if the alternative refreshconfiguration corresponds to an increased refresh rate, the memorydevice may increase the refresh operation periodicity, increase thequantity of rows of the memory array refreshed during each refreshoperation, or both.

At 425, the memory device may identify whether a reset operation hasbeen indicated by the host device. The reset operation may correspond toresetting the memory device from the alternative refresh configurationto the default configuration. When the memory device determines that thereset operation has been indicated, the memory device may proceed toblock 405, where the memory device will operate according to the defaultrefresh configuration (e.g., according to a set of refresh parameterspreconfigured for the memory device). Alternatively, when the memorydevice determines that the reset operation has not been indicated, thememory device may proceed to block 420 (e.g., the memory device maycontinue to operate according to the refresh parameters defined by thealternative refresh configuration).

FIG. 5 illustrates an example of a process flow 500 that refresh ratecontrol for a memory device as disclosed herein. The process flow 500may implement aspects of the systems 100 and 300 and memory die 200described with reference to FIGS. 1 through 3. The process flow 500 mayinclude operations performed by a host device 505, which may be anexample of host device 305 as described with reference to FIG. 3. Hostdevice 505 may implement aspects of the external memory controller 105as described with reference to FIG. 1. The process flow 500 may furtherinclude operations performed by a memory device 510, which may be anexample of the memory device 110, the memory array 170, or the memorydie 200, or the memory device 310 as described with reference to FIGS. 1through 3.

At 515, the memory device 510 may operate a memory array of the memorydevice 510 according to a first refresh mode or configuration. Operatingthe memory array of the memory device 510 according to the first refreshmode may include the memory device 510 operating the memory according toa first set of refresh parameters corresponding to a first rate forrefreshing the memory array. The first set of refresh parameters mayinclude a first quantity of rows that are refreshed for each refreshoperation. The memory device 510 may determine the first quantity ofrows and a first refresh periodicity. Here, operating the memory arrayaccording to the first set of refresh parameters may include performingrefresh operations at the first refresh periodicity. In some instances,the memory device 510 may receive a plurality of refresh commands fromthe host device 505. Here, the memory device 510 may operate the memoryarray according to the first set of refresh parameters by performing onerefresh operation for each of the plurality of refresh commands. In somecases, the first refresh mode may correspond to a default refreshoperation mode. That is, when the first refresh parameters maycorrespond to some preconfigured refresh parameters.

At 520, the memory device 510 may detect an event. The event may beassociated with a reduction in data integrity at the memory array. Forexample, the event may correspond to one or more of a voltage condition,a data error condition, a minimum refresh rate, or a status of one ormore components of the memory array. In some cases, the memory device510 may determine that a temperature of the memory device 510 satisfiesa threshold. Here, the memory device 510 may detect the event based ondetermining that the temperature satisfies the threshold. In some cases,the data error condition may be based on a rate of error corrections fora circuit initiating error correction on data stored in the memoryarray.

At 525, the memory device 510 may operate the memory array according toa second refresh mode. Operating the memory device 510 according to thesecond refresh mode may include the memory device 510 operating thememory array according to a second set of refresh parameters based atleast in part on detecting the event, the second set of refreshparameters corresponding to a second rate for refreshing the memoryarray that is higher than (e.g., faster than) the first rate. The secondset of refresh parameters may include a second quantity of rows that arerefreshed for each refresh operation. In some cases, the memory device510 may determine the second quantity of rows and a second refreshperiodicity based on detecting the event. Here, operating the memoryarray according to the second set of refresh parameters may includeperforming the plurality of refresh operation at the second refreshperiodicity. In some cases, the memory device 510 may switch,autonomously from the host device 505, from operating according to thefirst set of refresh parameters to operating according to the second setof refresh parameters based on detecting the event at the memory device510. In some instances, the memory device 510 may receive a plurality ofrefresh commands from the host device 505. Here, the memory device 510may operate the memory array according to the second set of refreshparameters by performing one refresh operation for each of the pluralityof refresh commands. The second refresh mode may correspond to analternate refresh operation as disclosed herein.

At 530, the memory device 510 may transmit an indication of the secondrefresh operation to the host device 505. That is, the memory device 510may transmit signaling including an indication of operating the memoryarray according to the second set of refresh parameters based ondetecting the event at the memory array (e.g., as discussed at 520). Insome cases, the signaling may include one or more bits indicative of theevent.

At 535, the memory device 510 may receive an indication of a thirdrefresh mode (e.g., corresponding to a third set of refresh parameters)from the host device 505. That is, the memory device 510 may receive anindication to operate the memory array according to the third set ofrefresh parameters while operating the memory array according to thesecond set of refresh parameters.

At 540, the memory device 510 may operate according to a third refreshmode based on receiving the indication from the host device 505 (e.g.,as discussed at 535). The third refresh mode may correspond to a thirdset of refresh parameters. In some cases, the third refresh mode may bethe same as the first refresh mode. Here, the indication may indicate areset operation where the memory device 510 may adapt to the firstrefresh parameters (e.g., and operate according to a default refreshoperation mode).

FIG. 6 illustrates an example of a process flow 600 that refresh ratecontrol for a memory device as disclosed herein. The process flow 600may implement aspects of the systems 100 and 300 and memory die 200described with reference to FIGS. 1 through 3. The process flow 600 mayinclude operations performed by a host device 605, which may be anexample of host device 305 as described with reference to FIG. 3. Hostdevice 605 may implement aspects of the external memory controller 105as described with reference to

FIG. 1. The process flow 600 may further include operations performed bya memory device 610, which may be an example of the memory device 110,the memory array 170, or the memory die 200, or the memory device 310 asdescribed with reference to FIGS. 1 through 3.

At 615, the memory device 610 may receive, from the host device 605, aplurality of refresh commands for a memory array of the memory device610.

At 620, the memory device may execute, at the memory array, a refreshcommand according to a first refresh mode. Executing a refresh commandaccording to the first refresh mode may correspond to executing therefresh command according to a first set of refresh parameters. Thefirst set of refresh parameters may include a first quantity of rows ofthe memory array that are refreshed during an execution of the firstrefresh command.

At 625, the memory device 610 may detect a condition of the memory array(e.g., associated with a reduction in data integrity). The condition maycorrespond to one or more of a temperature condition, a voltagecondition, a data error condition, a minimum refresh command rate, or acondition of one or more components of the memory device 610.

At 630, the memory device 610 may transition to a second refresh modebased on detecting the condition. That is, the memory device 610 maytransition from using the first set of refresh parameters to using asecond set of refresh parameters (e.g., according to the second refreshmode) corresponding to an increased refresh rate. The second set ofrefresh parameters may include a second quantity of rows of the memoryarray that are refreshed during an execution of the second refreshcommand, wherein the second quantity of rows is greater than the firstquantity of rows.

At 635, the memory device 610 may transmit an indication of thetransition to the host device 605. The indication may indicate thedetermining to transition the memory array to the second set of refreshparameters. In some cases, the indication may include the conditiondetected by the memory device 610.

At 640, the memory device 610 may execute a second refresh commandaccording to the second set of refresh parameters.

At 645, the memory device 610 may receive, from the host device 605, anindication of a third refresh mode. The indication may include signalingto transition the memory array from the second set of refresh parametersto a third set of refresh parameters, where the third set of refreshparameters may correspond to the third refresh mode. In some cases, thethird set of refresh parameters may be the same as the first set ofrefresh parameters. Here, the indication may include a reset indicationwhich may indicate to the memory device 610 to reset the refreshparameters to the first refresh parameters (which may correspond to aset of preconfigured refresh parameters).

At 650, the memory device 610 may execute a third refresh commandaccording to the third refresh mode. The memory device 610 may executethe third refresh command at the memory array according to the third setof refresh parameters based on the indication of the third refresh modereceived from the host device 605.

FIG. 7 shows a block diagram 700 of a device 705 that supports refreshrate control for a memory device as disclosed herein. The device 705 maybe an example of aspects of memory device 110, memory device 310, memorydevice 510, and memory device 610 as disclosed herein with reference toFIGS. 1, 3, 5, and 6. The device 705 may include a refresh mode manager710, an event detector 715, a refresh configuration 720, a refresh modetransition manager 725, a refresh command manager 730, and an indicationtransmitter 735. Each of these modules may communicate, directly orindirectly, with one another (e.g., via one or more buses).

The refresh mode manager 710 may operate a memory array of a memorydevice according to a first set of refresh parameters of the refreshconfiguration 720 corresponding to a first rate for refreshing thememory array. The refresh configuration 720 may store, for example, oneor more refresh configurations (e.g., sets of refresh parameters), andmay have predetermined (e.g., default) values for the sets of refreshparameters, or may have programmable sets of refresh parameters that maybe configured by a host device. In some cases, the first set of refreshparameters include a first quantity of rows that are refreshed for eachof a set of refresh operations. In some examples, the refresh modemanager 710 may determine the first quantity of rows and a first refreshperiodicity, where operating the memory array according to the first setof refresh parameters includes performing the set of refresh operationsat the first refresh periodicity.

The refresh mode manager 710 may execute, at the memory array, a firstrefresh command of the set of refresh commands according to a first setof refresh parameters of the refresh configuration 720. In some cases,the first set of refresh parameters includes a first quantity of rows ofthe memory array that are refreshed during an execution of the firstrefresh command.

The event detector 715 may detect, at the memory device, an event (e.g.,associated with a reduction in data integrity at the memory array)corresponding to at least one of a voltage condition, a data errorcondition, a minimum refresh rate, or a status of one or more componentsof the memory array. In some examples, the event detector 715 maydetermine, by the memory device, that a temperature of the memory devicesatisfies a threshold, where detecting the event at the memory array isbased on determining that the temperature of the memory device satisfiesthe threshold. In some cases, the data error condition is based on arate of error corrections for a circuit initiating error correction ondata stored in the memory array.

The event detector 715 may detect, at the memory device, a condition ofthe memory array (e.g., associated with a reduction in data integrity).In some cases, the condition corresponds to one or more of a temperaturecondition, a voltage condition, a data error condition, a minimumrefresh command rate, or a condition of one or more components of thememory device.

The refresh mode manager 710 may operate the memory array according to asecond set of refresh parameters of the refresh configuration 720 basedon detecting the event, the second set of refresh parameterscorresponding to a second rate for refreshing the memory array that isfaster than the first rate. In some cases, the second set of refreshparameters include a second quantity of rows that are refreshed for eachof the set of refresh operations. In some examples, the refresh modemanager 710 may determine, based on detecting the event at the memoryarray, the second quantity of rows and a second refresh periodicity,where operating the memory array according to the second set of refreshparameters includes performing the set of refresh operations at thesecond refresh periodicity.

The refresh mode manager 710 may execute, at the memory array, a secondrefresh command of the set of refresh commands according to the secondset of refresh parameters of the refresh configuration 720. In somecases, the second set of refresh parameters includes a second quantityof rows of the memory array that are refreshed during an execution ofthe second refresh command, where the second quantity of rows is greaterthan the first quantity of rows.

The refresh mode transition manager 725 may switch, by the memory device(e.g., autonomously from a host device), from operating according to thefirst set of refresh parameters to operating according to the second setof refresh parameters based on detecting the event at the memory device.The refresh mode transition manager 725 may transition, based ondetecting the condition, from using the first set of refresh parametersto using a second set of refresh parameters corresponding to anincreased refresh rate.

The refresh command manager 730 may receive, from a host device, a setof refresh commands, where operating the memory array according to thefirst set of refresh parameters or the second set of refresh parametersincludes performing one of the set of refresh operations for each of theset of refresh commands. The refresh command manager 730 may receive,from a host device, a set of refresh commands for a memory array of amemory device.

The indication transmitter 735 may transmit, to a host device based ondetecting the event at the memory array, signaling including anindication of operating the memory array according to the second set ofrefresh parameters. In some cases, the signaling includes one or morebits indicative of the event. The indication transmitter 735 maytransmit, to the host device and based on determining to transition thememory array from the first set of refresh parameters to the second setof refresh parameters, an indication of the determining to transitionthe memory array to the second set of refresh parameters. In someexamples, the indication transmitter 735 may transmit, to the hostdevice, an indication of the condition detected by the memory device.

The refresh mode manager 710 may receive, from a host device whileoperating the memory array according to the second set of refreshparameters, an indication to operate the memory array according to athird set of refresh parameters. In some examples, the refresh modemanager 710 may operate the memory array according to the third set ofrefresh parameters of the refresh configuration based on receiving theindication from the host device. The refresh mode manager 710 mayreceive, from the host device, signaling including an indication totransition the memory array from the second set of refresh parameters toa third set of refresh parameters. In some examples, the refresh modemanager 710 may execute, at the memory array, a third refresh command ofthe set of refresh commands according to the third set of refreshparameters based on signaling received from the host device.

FIG. 8 shows a flowchart illustrating a method 800 that supports refreshrate control for a memory device as disclosed herein. The operations ofmethod 800 may be implemented by a memory device (e.g., memory device110, memory device 310, memory device 510, and memory device 610 asdisclosed herein with reference to FIGS. 1, 3, 5, and 6) or itscomponents as described herein. For example, the operations of method800 may be performed by a device as described with reference to FIG. 7.In some examples, a memory device may execute a set of instructions tocontrol the functional elements of the memory device to perform thedescribed functions. Additionally or alternatively, a memory device mayperform aspects of the described functions using special-purposehardware.

At 805, the memory device may operate a memory array of the memorydevice according to a first set of refresh parameters corresponding to afirst rate for refreshing the memory array. The operations of 805 may beperformed according to the methods described herein. In some examples,aspects of the operations of 805 may be performed by a refresh modemanager as described with reference to FIG. 7.

At 810, the memory device may detect an event corresponding to at leastone of a voltage condition, a data error condition, a minimum refreshrate, or a status of one or more components of the memory array. Theoperations of 810 may be performed according to the methods describedherein. In some examples, aspects of the operations of 810 may beperformed by an event detector as described with reference to FIG. 7.

At 815, the memory device may operate the memory array according to asecond set of refresh parameters based on detecting the event, thesecond set of refresh parameters corresponding to a second rate forrefreshing the memory array that is faster than the first rate. Theoperations of 815 may be performed according to the methods describedherein. In some examples, aspects of the operations of 815 may beperformed by a refresh mode manager as described with reference to FIG.7.

Some examples of the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions foroperating a memory array of a memory device according to a first set ofrefresh parameters corresponding to a first rate for refreshing thememory array, detecting, by the memory device, an event corresponding toat least one of a voltage condition, a data error condition, a minimumrefresh rate, or a status of one or more components of the memory array,and operating the memory array according to a second set of refreshparameters based on detecting the event, the second set of refreshparameters corresponding to a second rate for refreshing the memoryarray that is faster than the first rate.

Some examples of the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions forswitching, by the memory device and autonomously from a host device,from operating according to the first set of refresh parameters tooperating according to the second set of refresh parameters based ondetecting the event at the memory device.

Some cases of the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions fordetermining, by the memory device, that a temperature of the memorydevice satisfies a threshold, where detecting the event at the memoryarray may be based on determining that the temperature of the memorydevice satisfies the threshold.

In some examples of the method 800 and the apparatus described hereinthe first set of refresh parameters include a first quantity of rowsthat may be refreshed for each of a set of refresh operations, and thesecond set of refresh parameters include a second quantity of rows thatmay be refreshed for each of the set of refresh operations.

In some instances, the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions fordetermining, by the memory device, the first quantity of rows and afirst refresh periodicity, where operating the memory array according tothe first set of refresh parameters includes performing the set ofrefresh operations at the first refresh periodicity, and determining, bythe memory device and based on detecting the event at the memory array,the second quantity of rows and a second refresh periodicity, whereoperating the memory array according to the second set of refreshparameters includes performing the set of refresh operations at thesecond refresh periodicity.

In some examples, the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions forreceiving, from a host device, a set of refresh commands, whereoperating the memory array according to the first set of refreshparameters or the second set of refresh parameters includes performingone of the set of refresh operations for each of the set of refreshcommands.

In some cases of the method 800 and the apparatus described herein thedata error condition may be based on a rate of error corrections for acircuit initiating error correction on data stored in the memory array.

In some instances, the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions fortransmitting, to a host device based on detecting the event at thememory array, signaling including an indication of operating the memoryarray according to the second set of refresh parameters.

In some examples of the method 800 and the apparatus described hereinthe signaling includes one or more bits indicative of the event.

Some examples of the method 800 and the apparatus described herein mayfurther include operations, features, means, or instructions forreceiving, from a host device while operating the memory array accordingto the second set of refresh parameters, an indication to operate thememory array according to a third set of refresh parameters, andoperating the memory array according to the third set of refreshparameters based on receiving the indication from the host device.

FIG. 9 shows a flowchart illustrating a method 900 that supports refreshrate control for a memory device as disclosed herein. The operations ofmethod 900 may be implemented by a memory device (e.g., memory device110, memory device 310, memory device 510, and memory device 610 asdisclosed herein with reference to FIGS. 1, 3, 5, and 6) or itscomponents as described herein. For example, the operations of method900 may be performed by a device as described with reference to FIG. 7.In some examples, a memory device may execute a set of instructions tocontrol the functional elements of the memory device to perform thedescribed functions. Additionally or alternatively, a memory device mayperform aspects of the described functions using special-purposehardware.

At 905, the memory device may operate a memory array of the memorydevice according to a first set of refresh parameters corresponding to afirst rate for refreshing the memory array. The operations of 905 may beperformed according to the methods described herein. In some examples,aspects of the operations of 905 may be performed by a refresh modemanager as described with reference to FIG. 7.

At 910, the memory device may detect an event corresponding to at leastone of a voltage condition, a data error condition, a minimum refreshrate, or a status of one or more components of the memory array. Theoperations of 910 may be performed according to the methods describedherein. In some examples, aspects of the operations of 910 may beperformed by an event detector as described with reference to FIG. 7.

At 915, the memory device may switch from operating according to thefirst set of refresh parameters to operating according to the second setof refresh parameters based on detecting the event at the memory device.The operations of 915 may be performed according to the methodsdescribed herein. In some examples, aspects of the operations of 915 maybe performed by a refresh mode transition manager as described withreference to FIG. 7.

At 920, the memory device may operate the memory array according to asecond set of refresh parameters based on detecting the event, thesecond set of refresh parameters corresponding to a second rate forrefreshing the memory array that is faster than the first rate. Theoperations of 920 may be performed according to the methods describedherein. In some examples, aspects of the operations of 920 may beperformed by a refresh mode manager as described with reference to FIG.7.

At 925, the memory device may transmit, to a host device based ondetecting the event at the memory array, signaling including anindication of operating the memory array according to the second set ofrefresh parameters. The operations of 925 may be performed according tothe methods described herein. In some examples, aspects of theoperations of 925 may be performed by an indication transmitter asdescribed with reference to FIG. 7.

FIG. 10 shows a flowchart illustrating a method 1000 that supportsrefresh rate control for a memory device as disclosed herein. Theoperations of method 1000 may be implemented by a memory device (e.g.,memory device 110, memory device 310, memory device 510, and memorydevice 610 as disclosed herein with reference to FIGS. 1, 3, 5, and 6)or its components as described herein. For example, the operations ofmethod 1000 may be performed by a device as described with reference toFIG. 7. In some examples, a memory device may execute a set ofinstructions to control the functional elements of the memory device toperform the described functions. Additionally or alternatively, a memorydevice may perform aspects of the described functions usingspecial-purpose hardware.

At 1005, the memory device may receive, from a host device, a set ofrefresh commands for a memory array of the memory device. The operationsof 1005 may be performed according to the methods described herein. Insome examples, aspects of the operations of 1005 may be performed by arefresh command manager as described with reference to FIG. 7.

At 1010, the memory device may execute, at the memory array, a firstrefresh command of the set of refresh commands according to a first setof refresh parameters. The operations of 1010 may be performed accordingto the methods described herein. In some examples, aspects of theoperations of 1010 may be performed by a refresh mode manager asdescribed with reference to FIG. 7.

At 1015, the memory device may detect a condition of the memory array(e.g., associated with a reduction in data integrity). The operations of1015 may be performed according to the methods described herein. In someexamples, aspects of the operations of 1015 may be performed by an eventdetector as described with reference to FIG. 7.

At 1020, the memory device may transition, based on detecting thecondition, from using the first set of refresh parameters to using asecond set of refresh parameters corresponding to an increased refreshrate. The operations of 1020 may be performed according to the methodsdescribed herein. In some examples, aspects of the operations of 1020may be performed by a refresh mode transition manager as described withreference to FIG. 7.

At 1025, the memory device may execute, at the memory array, a secondrefresh command of the set of refresh commands according to the secondset of refresh parameters. The operations of 1025 may be performedaccording to the methods described herein. In some examples, aspects ofthe operations of 1025 may be performed by a refresh mode manager asdescribed with reference to FIG. 7.

Some examples of the method 1000 and the apparatus described herein mayfurther include operations, features, means, or instructions forreceiving, from a host device, a set of refresh commands for a memoryarray of a memory device, executing, at the memory array, a firstrefresh command of the set of refresh commands according to a first setof refresh parameters, detecting, by the memory device, a condition ofthe memory array associated with a reduction in data integrity,transitioning, based on detecting the condition, from using the firstset of refresh parameters to using a second set of refresh parameterscorresponding to an increased refresh rate, and executing, at the memoryarray, a second refresh command of the set of refresh commands accordingto the second set of refresh parameters.

In some examples of the method 1000 and the apparatus described hereinthe first set of refresh parameters includes a first quantity of rows ofthe memory array that may be refreshed during an execution of the firstrefresh command, and the second set of refresh parameters includes asecond quantity of rows of the memory array that may be refreshed duringan execution of the second refresh command, where the second quantity ofrows may be greater than the first quantity of rows.

In some cases of the method 1000 and the apparatus described herein thecondition corresponds to one or more of a temperature condition, avoltage condition, a data error condition, a minimum refresh commandrate, or a condition of one or more components of the memory device.

Some instances of the method 1000 and the apparatus described herein mayfurther include operations, features, means, or instructions fortransmitting, to the host device and based on determining to transitionthe memory array from the first set of refresh parameters to the secondset of refresh parameters, an indication of the determining totransition the memory array to the second set of refresh parameters.

Some examples of the method 1000 and the apparatus described herein mayfurther include operations, features, means, or instructions fortransmitting, to the host device, an indication of the conditiondetected by the memory device.

Some cases of the method 1000 and the apparatus described herein mayfurther include operations, features, means, or instructions forreceiving, from the host device, signaling including an indication totransition the memory array from the second set of refresh parameters toa third set of refresh parameters, and executing, at the memory array, athird refresh command of the set of refresh commands according to thethird set of refresh parameters based on signaling received from thehost device.

FIG. 11 shows a flowchart illustrating a method 1100 that supportsrefresh rate control for a memory device as disclosed herein. Theoperations of method 1100 may be implemented by a memory device (e.g.,memory device 110, memory device 310, memory device 510, and memorydevice 610 as disclosed herein with reference to FIGS. 1, 3, 5, and 6)or its components as described herein. For example, the operations ofmethod 1100 may be performed by a device as described with reference toFIG. 7. In some examples, a memory device may execute a set ofinstructions to control the functional elements of the memory device toperform the described functions. Additionally or alternatively, a memorydevice may perform aspects of the described functions usingspecial-purpose hardware.

At 1105, the memory device may receive, from a host device, a set ofrefresh commands for a memory array of a memory device. The operationsof 1105 may be performed according to the methods described herein. Insome examples, aspects of the operations of 1105 may be performed by arefresh command manager as described with reference to FIG. 7.

At 1110, the memory device may execute, at the memory array, a firstrefresh command of the set of refresh commands according to a first setof refresh parameters. The first set of refresh parameters may include afirst quantity of rows of the memory array that are refreshed during anexecution of the first refresh command. The operations of 1110 may beperformed according to the methods described herein. In some examples,aspects of the operations of 1110 may be performed by a refresh modemanager as described with reference to FIG. 7.

At 1115, the memory device may detect, by the memory device, a conditionof the memory array (e.g., associated with a reduction in dataintegrity). The operations of 1115 may be performed according to themethods described herein. In some examples, aspects of the operations of1115 may be performed by an event detector as described with referenceto

FIG. 7.

At 1120, the memory device may transition, based on detecting thecondition, from using the first set of refresh parameters to using asecond set of refresh parameters corresponding to an increased refreshrate. The operations of 1120 may be performed according to the methodsdescribed herein. In some examples, aspects of the operations of 1120may be performed by a refresh mode transition manager as described withreference to FIG. 7.

At 1125, the memory device may execute, at the memory array, a secondrefresh command of the set of refresh commands according to the secondset of refresh parameters. The second set of refresh parameters mayinclude a second quantity of rows of the memory array that are refreshedduring an execution of the second refresh command, where the secondquantity of rows is greater than the first quantity of rows. Theoperations of 1125 may be performed according to the methods describedherein. In some examples, aspects of the operations of 1125 may beperformed by a refresh mode manager as described with reference to FIG.7.

At 1130, the memory device may transmit, to the host device and based ondetermining to transition the memory array from the first set of refreshparameters to the second set of refresh parameters, an indication of thedetermining to transition the memory array to the second set of refreshparameters. The operations of 1140 may be performed according to themethods described herein. In some examples, aspects of the operations of1140 may be performed by an indication transmitter as described withreference to FIG. 7.

It should be noted that the methods described herein describe possibleimplementations, and that the operations and the steps may be rearrangedor otherwise modified and that other implementations are possible.Further, aspects from two or more of the methods may be combined.

In some examples, an apparatus configured for refresh rate control for amemory device may perform aspects of the function described herein usinggeneral- or special-purpose hardware. The apparatus may include aprocessor, memory in electronic communication with the processor, andinstructions stored in the memory. The instructions may be executable bythe processor to cause the apparatus to a memory array having a set ofrows of memory cells, a memory interface coupled with the memory arrayand configured to periodically receive, from a host, a set of commandsfor refreshing rows of the memory array, circuitry coupled with thememory array and the memory interface, the circuitry operable to causethe apparatus to identify a target rate for refreshing the memory arraybased on a detected event (e.g., an event associated with a reduction indata integrity at the memory array), determine that a rate associatedwith the set of commands for refreshing the memory array does notsatisfy the target rate, and adjust one or more parameters related torefreshing the rows of memory cells during an execution of a command ofthe set of commands for refreshing the rows of the memory array tosatisfy the target rate.

In some cases, the detected event corresponds to one or more of atemperature event, a determined voltage condition, an error event, aminimum rate for refreshing the memory array, and a status of one ormore components of the apparatus.

In some examples, the memory interface may be further configured totransmit, to the host and based on the determining that the rate doesnot satisfy the target rate, signaling that indicates the adapting ofthe one or more parameters.

In some instances, the memory interface may be further configured totransmit the signaling that indicates the detected event at the memoryarray.

Although certain features may be described herein with respect to or inthe context of DRAM technology, this is for illustrative purposes only,and one of ordinary skill in the art will appreciate that the teachingsherein may be applied to any type of memory device. For example, theteachings herein may be applied to volatile or non-volatile memorydevices such as magnetic hard disks, random access memory (RAM),read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM(SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM(RRAM), flash memory, phase change memory (PCM), and others.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, any combinationthereof, or the like. Some drawings may illustrate signals as a singlesignal; however, it will be understood by a person of ordinary skill inthe art that the signal may represent a bus of signals, where the busmay have a variety of bit widths.

As used herein, the term “virtual ground” refers to a node of anelectrical circuit that is held at a voltage of approximately zero volts(0V) but that is not directly coupled with ground. Accordingly, thevoltage of a virtual ground may temporarily fluctuate and return toapproximately 0V at steady state. A virtual ground may be implementedusing various electronic circuit elements, such as a voltage dividerconsisting of operational amplifiers and resistors. Otherimplementations are also possible. “Virtual grounding” or “virtuallygrounded” means connected to approximately 0V.

The terms “electronic communication,” “conductive contact,” “connected,”and “coupled” may refer to a relationship between components thatsupports the flow of signals between the components. Components areconsidered in electronic communication with (or in conductive contactwith or connected with or coupled with) one another if there is anyconductive path between the components that can, at any time, supportthe flow of signals between the components. At any given time, theconductive path between components that are in electronic communicationwith each other (or in conductive contact with or connected with orcoupled with) may be an open circuit or a closed circuit based on theoperation of the device that includes the connected components. Theconductive path between connected components may be a direct conductivepath between the components or the conductive path between connectedcomponents may be an indirect conductive path that may includeintermediate components, such as switches, transistors, or othercomponents. In some cases, the flow of signals between the connectedcomponents may be interrupted for a time, for example, using one or moreintermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuitrelationship between components in which signals are not presentlycapable of being communicated between the components over a conductivepath to a closed-circuit relationship between components in whichsignals are capable of being communicated between components over theconductive path. When a component, such as a controller, couples othercomponents together, the component initiates a change that allowssignals to flow between the other components over a conductive path thatpreviously did not permit signals to flow.

The term “isolated” refers to a relationship between components in whichsignals are not presently capable of flowing between the components.Components are isolated from each other if there is an open circuitbetween them. For example, two components separated by a switch that ispositioned between the components are isolated from each other when theswitch is open. When a controller isolates two components, thecontroller affects a change that prevents signals from flowing betweenthe components using a conductive path that previously permitted signalsto flow.

The devices discussed herein, including a memory array, may be formed ona semiconductor substrate, such as silicon, germanium, silicon-germaniumalloy, gallium arsenide, gallium nitride, etc. In some cases, thesubstrate is a semiconductor wafer. In other cases, the substrate may bea silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG)or silicon-on-sapphire (SOP), or epitaxial layers of semiconductormaterials on another substrate. The conductivity of the substrate, orsub-regions of the substrate, may be controlled through doping usingvarious chemical species including, but not limited to, phosphorous,boron, or arsenic. Doping may be performed during the initial formationor growth of the substrate, by ion-implantation, or by any other dopingmeans.

A switching component or a transistor discussed herein may represent afield-effect transistor (FET) and comprise a three terminal deviceincluding a source, drain, and gate. The terminals may be connected toother electronic elements through conductive materials, e.g., metals.The source and drain may be conductive and may comprise a heavily-doped,e.g., degenerate, semiconductor region. The source and drain may beseparated by a lightly-doped semiconductor region or channel. If thechannel is n-type (i.e., majority carriers are signals), then the FETmay be referred to as a n-type FET. If the channel is p-type (i.e.,majority carriers are holes), then the FET may be referred to as ap-type FET. The channel may be capped by an insulating gate oxide. Thechannel conductivity may be controlled by applying a voltage to thegate. For example, applying a positive voltage or negative voltage to ann-type FET or a p-type FET, respectively, may result in the channelbecoming conductive.

A transistor may be “on” or “activated” when a voltage greater than orequal to the transistor's threshold voltage is applied to the transistorgate. The transistor may be “off” or “deactivated” when a voltage lessthan the transistor's threshold voltage is applied to the transistorgate.

The description set forth herein, in connection with the appendeddrawings, describes example configurations and does not represent allthe examples that may be implemented or that are within the scope of theclaims. The term “exemplary” used herein means “serving as an example,instance, or illustration,” and not “preferred” or “advantageous overother examples.” The detailed description includes specific details toproviding an understanding of the described techniques. Thesetechniques, however, may be practiced without these specific details. Insome instances, well-known structures and devices are shown in blockdiagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If just the firstreference label is used in the industry standard or specification, thedescription may be applicable to any one of the similar componentshaving the same first reference label irrespective of the secondreference label.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, any combinationthereof, or the like.

The various illustrative blocks and modules described in connection withthe disclosure herein may be implemented or performed with ageneral-purpose processor, a DSP, an ASIC, an FPGA or other programmablelogic device, discrete gate or transistor logic, discrete hardwarecomponents, or the like, or any combination thereof designed to performthe functions described herein. A general-purpose processor may be amicroprocessor, but in the alternative, the processor may be anyprocessor, controller, microcontroller, or state machine. A processormay also be implemented as a combination of computing devices (e.g., acombination of a DSP and a microprocessor, multiple microprocessors, oneor more microprocessors in conjunction with a DSP core, or any othersuch configuration).

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or the like, or any combinationthereof. If implemented in software executed by a processor, thefunctions may be stored on or transmitted over as one or moreinstructions or code on a computer-readable medium. Other examples andimplementations are within the scope of the disclosure and appendedclaims. For example, due to the nature of software, functions describedabove can be implemented using software executed by a processor,hardware, firmware, hardwiring, or the like, or combinations of any ofthese. Features implementing functions may also be physically located atvarious positions, including being distributed such that portions offunctions are implemented at different physical locations. Also, as usedherein, including in the claims, “or” as used in a list of items (forexample, a list of items prefaced by a phrase such as “at least one of”or “one or more of”) indicates an inclusive list such that, for example,a list of at least one of A, B, or C means A or B or C or AB or AC or BCor ABC (i.e., A and B and C). Also, as used herein, the phrase “basedon” shall not be construed as a reference to a closed set of conditions.For example, an exemplary step that is described as “based on conditionA” may be based on both a condition A and a condition B withoutdeparting from the scope of the present disclosure. In other words, asused herein, the phrase “based on” shall be construed in the same manneras the phrase “based at least in part on.”

The description herein is provided to enable a person skilled in the artto make or use the disclosure. Various modifications to the disclosurewill be apparent to those skilled in the art, and the generic principlesdefined herein may be applied to other variations without departing fromthe scope of the disclosure. Thus, the disclosure is not limited to theexamples and designs described herein, but is to be accorded thebroadest scope consistent with the principles and novel featuresdisclosed herein.

What is claimed is:
 1. An apparatus, comprising: a memory array having aplurality of rows of memory cells; a memory interface coupled with thememory array and configured to periodically receive, from a host, aplurality of commands for refreshing rows of the memory array; andcircuitry coupled with the memory array and the memory interface, thecircuitry operable to cause the apparatus to: identify a target rate forrefreshing the memory array based at least in part on a detected event;determine that a rate associated with the plurality of commands forrefreshing the memory array does not satisfy the target rate; and adjustone or more parameters related to refreshing rows of memory cells duringan execution of a command of the plurality of commands for refreshingthe rows of the memory array to satisfy the target rate.
 2. Theapparatus of claim 1, wherein the detected event corresponds to one ormore of a temperature event, a determined voltage condition, an errorevent, a minimum rate for refreshing the memory array, and a status ofone or more components of the apparatus.
 3. The apparatus of claim 1,wherein the memory interface is further configured to transmit, to thehost and based at least in part on the determining that the rate doesnot satisfy the target rate, signaling that indicates the adjusting ofthe one or more parameters.
 4. The apparatus of claim 1, wherein thecircuitry is operable to cause the apparatus to determine that atemperature of the memory array fails to satisfy a threshold and toidentify the detected event based at least in part on determining thatthe temperature fails to satisfy the threshold, wherein identifying thetarget rate is based at least in part on identifying the detected event.5. The apparatus of claim 1, wherein the circuitry is operable to causethe apparatus to determine that a voltage level of a power supply forthe memory array fails to satisfy a threshold and to identify thedetected event based at least in part on determining that the voltagelevel fails to satisfy the threshold, wherein identifying the targetrate is based at least in part on identifying the detected event.
 6. Theapparatus of claim 1, the circuitry is operable to cause the apparatusto determine that a quantity of error correction operations exceeds athreshold and to identify the detected event based at least in part ondetermining that the quantity of error correction operations exceeds thethreshold, wherein identifying the target rate is based at least in parton identifying the detected event.
 7. A method, comprising: receiving,from a host, a plurality of commands for refreshing rows of a memoryarray; identifying a target rate for refreshing the memory array basedat least in part on a detected event; determining that a rate associatedwith the plurality of commands for refreshing the memory array fails tosatisfy the target rate; and adjusting one or more parameters related torefreshing rows of memory cells during an execution of a command of theplurality of commands for refreshing the rows of the memory array tosatisfy the target rate.
 8. The method of claim 7, wherein the detectedevent corresponds to one or more of a temperature event, a determinedvoltage condition, an error event, a minimum rate for refreshing thememory array, and a status of one or more components of the memoryarray.
 9. The method of claim 7, further comprising: transmitting, tothe host and based at least in part on the determining that the ratefails to satisfy the target rate, signaling that indicates the adjustingof the one or more parameters.
 10. The method of claim 9, furthercomprising: transmitting, to the host, the signaling that indicates thedetected event at the memory array.
 11. The method of claim 7, furthercomprising: determining the rate based at least in part on a refreshoperation execution periodicity and a quantity of rows of the memoryarray that are refreshed during the execution of each refresh operation.12. The method of claim 7, further comprising: identifying the detectedevent based at least in part on determining that the rate is less thanthe one or more parameters related to refreshing the rows of memorycells, wherein identifying the target rate for refreshing the memoryarray is based at least in part on identifying the detected event. 13.The method of claim 7, further comprising: detecting a degradation ofone or more components of the memory array; and identifying the detectedevent based at least in part on detecting the degradation of the one ormore components of the memory array, wherein identifying the target ratefor refreshing the memory array is based at least in part on identifyingthe detected event.
 14. The method of claim 7, wherein adjusting the oneor more parameters comprises: adapting a quantity of rows executedduring the execution of the command of the plurality of commands.
 15. Amethod, comprising: identifying a target rate for refreshing a memoryarray; determining whether a rate associated with a plurality ofoperations for refreshing the memory array satisfies the target rate;and adjusting one or more parameters for the plurality of operations forrefreshing the memory array based at least in part on determiningwhether the rate satisfies the target rate.
 16. The method of claim 15,further comprising: determining that the rate associated with theplurality of operations for refreshing the memory array fails to satisfythe target rate, wherein adjusting the one or more parameters is basedat least in part on determining that the rate fails to satisfy thetarget rate.
 17. The method of claim 15, wherein adjusting the one ormore parameters comprises: adapting a quantity of rows executed for eachof the plurality of operations for refreshing the memory array.
 18. Themethod of claim 15, wherein adjusting the one or more parameterscomprises: adapting a periodicity of the plurality of operations forrefreshing the memory array.
 19. The method of claim 15, whereindetermining whether the rate associated with the plurality of operationsfor refreshing the memory array satisfies the target rate comprises:determining whether a current refresh command periodicity will cause thememory array to receive a quantity of refresh commands over a timeperiod.
 20. The method of claim 15, wherein identifying the target rateis based at least in part on a temperature, a determined voltagecondition, an error event, a minimum rate for refreshing the memoryarray, and a status of one or more components of the memory array.